Semiconductor memory device having redundancy means
US4656610A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 1984 |
| Grant date | Apr 7, 1987 |
| Priority date | — |
| Expiry date | Jan 23, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/83
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The semiconductor memory device includes at least two memory arrays, a first selection circuit which selects a memory cell from either one of the memory arrays in accordance with address signals, preferably two spare memory arrays and a second selection circuit which selects a memory cell from either one of the spare memory arrays. If a defective memory cell or cells are contained in one of the two memory arrays, the second selection circuit an select a spare memory cell or cells from any of the two spare memory arrays in place of the defective memory cell or cells. Thus, the spare memory arrays can be used effectively. Two sets of main amplifiers are also disposed and only one of them, which receives the data from the memory cell selected from the memory arrays or spare memory arrays, is operated. Thus, lower power consumption can be realized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.