Clock frequency divider circuit
US4656649A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 18, 1985 |
| Grant date | Apr 7, 1987 |
| Priority date | — |
| Expiry date | Dec 18, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/68
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock frequency divider circuit for producing signals of a desired frequency (of, for example, 1.024 MHz) in response selectively to input clock pulses of two or more different predetermined frequencies, wherein control pulses are produced from and in synchronism with the input clock pulses and are fed to a frequency division network including two master-slave "D" flip-flop circuits adapted to produce a first predetermined fraction of the frequency of the control pulses in response to input clock pulses of a first frequency (of, for example, 2.048 MHz conforming to CCITT Recommendation standard) or a second predetermined fraction of the frequency of the control pulses in response to input clock pulses of a second or third frequency (of, for example, 1.536 MHz or 1.544 MHz conforming to T-1 standards). Signals with a frequency corresponding to such a first or second predetermined fraction are fed to a frequency selector network in which the frequency fraction is multiplied by a first or second predetermined multiple to achieve the desired frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.