Internally synchronous matrix structure for use in externally asynchronous programmable devices
US4658253A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 9, 1985 |
| Grant date | Apr 14, 1987 |
| Priority date | — |
| Expiry date | Oct 9, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1772
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The speed of operation of a programmable logic device which contains internally synchronous circuit structure is increased by an improved architecture which does not require a power-up transition cycle. Synchronous operation is carried out only for one transition. In each column of the matrix of programmable cells, the rows of which are coupled to receive the logic signals upon which the device is to operate, the programmable cells of that column are coupled via a respective inverter feedback pair to a column output link of the matrix. The connection between the programmable cells of the matrix and the inverter feedback pairs are coupled to pull-down switch devices control inputs of which are coupled to the output of an OR tie, inputs or which depend upon a prescribed transition on row input links. This transition is detected by respective transition detectors which trigger only on a particular transition edge. When the row inputs to the matrix change state, the column outputs follow the transitions asynchronously, with the only delay being that imparted by the inherent delay through the inverter feedback pairs. When the row inputs switch or transition to the opposite state, the tr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.