Compliant layer printed circuit board
US4658332A · kind A · utility
56Cited by
11References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 19, 1985 |
| Grant date | Apr 14, 1987 |
| Priority date | — |
| Expiry date | Sep 19, 2005 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/4913
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A printed circuit board having a compliant layer sandwiched between a pattern of conductors and an insulating layer. The printed circuit board has leadless chip carriers attached to soldering pads on the board using conventional soldering techniques. The elasticity of the compliant layer between the pattern of conductors and the insulating layer provides mechanical decoupling for minimizing stresses on the solder joints due to the different thermal coefficients of expansion of contiguous materials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.