Method for manufacturing VLSI MOS-transistor circuits

US4658496A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Willy Beinvogl · Munich, DE
• Gerhard Enders · Glen Allen, US
• Ernst Mohr · Murten, CH

Key dates

• Filing date: Oct 2, 1985
• Grant date: Apr 21, 1987
• Expiry date: Oct 2, 2005

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/90
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for manufacturing VLSI MOS-transistor circuits involving the production of transistors by means of a spacer layer technique and ohmic contacts from the gate interconnect to the diffused regions of the substrate (thus providing buried contacts) both being simultaneously generated. Contact holes are provided at the desired location in the substrate before the deposition of the spacer layer occurs across the surface of the substrate. The spacer layer is simultaneously structured at the side walls of the gates and at the side walls of the interconnects which serve as connections. The contact hole region is doped at the same time as the source/drain areas are provided by ion implantation. The combined manufacture of transistors using spacer technology and buried contacts makes it possible to manufacture MOS logic circuits and memory circuits with voltage stable transistors in high packing density.