Low defect etching of patterns using plasma-stencil mask
US4661203A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 1985 |
| Grant date | Apr 28, 1987 |
| Priority date | — |
| Expiry date | Jun 28, 2005 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/949
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Resist coating on the surface of a semiconductor wafer is removed by a one-step process using anisotropic reactive ion etching through an apertured stencil disposed close to but spaced from the resist-coated surface. The ion bombardment greatly enhances the plasma etch rate in the areas of the coating exposed through stencil apertures so that only the exposed areas are effectively etched during the limited exposure time in spite of the presence of chemically reactive gas between the stencil and other areas of the wafer surface. The technique is limited by low resolution but is ideally suited for clearing resist from atop fiducial marks used to align the wafer with multiple wafers in an integrated circuit chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.