Gate array integrated device having mixed single column type and matrix type arrays
US4661815A · kind A · utility
21Cited by
4References
10Claims
0Family size
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Key dates
| Filing date | Oct 2, 1985 |
| Grant date | Apr 28, 1987 |
| Priority date | — |
| Expiry date | Oct 2, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gate array integrated device including a plurality of single column type arrays, a plurality of matrix type arrays such as double column type arrays (BC2), and longitudinal connection areas (CH) provided between the single column type arrays and the matrix type arrays. One of the single column type arrays facing at least one side of each of the matrix type arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.