Programmed logic array with two-level control timing
US4661922A · kind A · utility
17Cited by
10References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 8, 1982 |
| Grant date | Apr 28, 1987 |
| Priority date | — |
| Expiry date | Dec 8, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17716
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmed logic array (PLA) is equipped with a first master-slave shift register on the intermediate wordlines (e.g., W.sub.1, W.sub.2 . . . W.sub.n) between AND and OR planes of the PLA and a second master-slave shift register on the output lines emanating from the OR plane. In this way, since the propagation delays of both AND and OR planes are much larger than those of the registers, the speed of operation of the PLA is limited to the greater of the propagation delays of the AND and OR plane instead of the sum of these delays as in prior art.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.