Salicide process for forming low sheet resistance doped silicon junctions
US4663191A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 1985 |
| Grant date | May 5, 1987 |
| Priority date | — |
| Expiry date | Oct 25, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32134
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process of forming a patterned silicide layer overlying a processed semiconductor substrate, the substrate having insulator regions and insulator-free regions on an exposed surface thereof, comprising the steps of: PA0 co-depositing silicon and a refractory metal on the exposed surface of the substrate to form a metal rich silicide thereon; PA0 annealing the metal rich silicide such that it reacts with the underlying insulator-free regions to form a reacted silicide without reacting with the underlying insulator regions; and PA0 exposing the substrate to a wet etchant which removes the unreacted portions of the metal rich silicide without removing the reacted silicide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.