Voltage level shifting depletion mode FET logical circuit
US4663543A · kind A · utility
17Cited by
3References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 19, 1985 |
| Grant date | May 5, 1987 |
| Priority date | — |
| Expiry date | Sep 19, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01714
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A GaAs D-MESFET logic system having a low power delay product has a switching second and a voltage level shifting section. The voltage level shifting section consists of a chain of diodes and a pulldown transistor. The switching section consists of an array of D-MESFETs which acts to speed up operation of a coupling capacitor. The low power dissipation of known capacitor coupled D-MESFET logic is thus preserved, while reducing gate delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.