Strobed access semiconductor memory system
US4663741A · kind A · utility
13Cited by
1References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 16, 1984 |
| Grant date | May 5, 1987 |
| Priority date | — |
| Expiry date | Oct 16, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/416
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit memory system having an array of ECL memory cells, an address circuit, a READ/WRITE circuit and a coupling circuit which increases the operating current of an addressed memory cell during a READ/WRITE operation. The increased operating current is short enough to prevent an excessive saturation of the memory cell transistors. The addressed memory cells remain in a low operating current sufficient to maintain the memory cells in their particular states. Since timing is critical, timing circuits for a system clock are also part of the memory system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.