Multiple clock power down method and structure
US4665328A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 27, 1984 |
| Grant date | May 12, 1987 |
| Priority date | — |
| Expiry date | Jul 27, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and structure is provided for powering down a plurality of clocks in a predetermined sequence. In one embodiment, a clock is powered down when it reaches a predefined logical level following the receipt of a power down signal. In another embodiment, a clock is powered down in response to a power down signal when the clock reaches a predefined level, and all clocks derived from that clock reach predefined levels. This is accomplished by including an edge sense circuit for determining when a clock reaches a predefined level, circuitry for combining a plurality of logical signals which indicate when the clock has reached said predefined level, and when all clocks derived from that clock have been powered down. Means and structure are also provided for powering down internal read/write control signals in response to a power down signal, thereby minimizing power consumption which would occur if the read/write control signals were switching during the power down cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.