Method and means for error detection and correction in high speed data transmission codes
US4665523A · kind A · utility
26Cited by
0References
4Claims
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Key dates
| Filing date | Feb 15, 1984 |
| Grant date | May 12, 1987 |
| Priority date | — |
| Expiry date | Feb 15, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/151
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and processing matrix for detection and correction of errors in coded data based on determining the error location and error evaluator polynomials using the relationship defined by the key equation. A systolic processor is disclosed which utilizes pipelining and a regular, parallel structure based on a derived algorithm for solving the key equation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.