Method for forming channel stops in vertical semiconductor surfaces
US4666557A · kind A · utility
21Cited by
9References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 10, 1984 |
| Grant date | May 19, 1987 |
| Priority date | — |
| Expiry date | Dec 10, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/665
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming channel stops in the sidewalls of a trench isolation structure formed in a semiconductor substrate. In one form, anistrophically etched substrate trenches are conformally covered by doped glass, the doped glass is anisotropically etched to retain vertical, sidewall segments of doped glass, and the substrate is annealed to form shallow diffusions in the trench sidewalls. The depth of the sidewall diffusion is related to differences in the dopant segregation coefficients between the glass and substrate materials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.