Semiconductor chip module interconnection system
US4667220A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 1984 |
| Grant date | May 19, 1987 |
| Priority date | — |
| Expiry date | Apr 27, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15173
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A module for a semiconductor chip having a front face with a two dimensional array of power, ground and signal contacts is disclosed. Power, ground and signal conductors extend from the respective contacts on the front face of the chip. A pair of electrically conductive plates are parallel to the front face of the chip and located at the termination of the conductors. The plate nearer the conductors is electrically coupled to either the power or ground conductors, and contains apertures corresponding to the remaining ground or power conductors and to the signal conductors. A plurality of discrete signal transmission members are located at a surface of the plate farther from the conductors. The ground or power conductors not connected to the near plate are electrically coupled to the far plate through certain of the apertures, and the signal conductors are coupled to the respective signal transmission members through the remaining apertures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.