Synchronizing circuit
US4669000A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 1985 |
| Grant date | May 26, 1987 |
| Priority date | — |
| Expiry date | Feb 12, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B27/3027
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
This invention relate to a synchronizing circuit for a data signal in which a data signal is divided at every predetermined number of bits, and every divided data signal is added with a synchronizing signal, an arbitrary address signal and an error detection signal for the address signal and received so as to be written in a memory in accordance with the address signal, which includes means (4) for detecting the synchronizing signal and means (3) for detecting an error of the address signal. The circuit further comprising an interpolation synchronizing signal generating circuit (6) and an interpolation address signal generating circuit (10), in which when the address signal is judged as being correct by the error detecting means (3), the interpolation synchronizing signal generating circuit (6) is driven, the interpolation address signal generating circuit (10) is driven by an interpolation synchronizing signal from the interpolation synchronizing signal generating circuit (6), and the address signal and the interpolation address signal are changed over on the basis of whether the address signal is correct or erroneous and then fed to the memory (13 ). According to this invention, …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.