Multiphase frequency selective phase locked loop with multiphase sinusoidal and digital outputs
US4669024A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 23, 1985 |
| Grant date | May 26, 1987 |
| Priority date | — |
| Expiry date | Oct 23, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/087
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for providing a multiphase digitally synthesized sinusoidal output signal representative of a predetermined symmetrical component set of a multiphase source signal and having a predetermined relationship therewith is taught. The circuit comprises a phase comparator, a phase shifter and a synthesizer. The phase comparator produces an output representative of the phase error in the predetermined phase relationship between the source signal and the output signal. The phase shifter has a variable frequency output for shifting the phase of the synthesized output signal in response to the phase error output signal of the phase comparator. The synthesizer digitally synthesizes at a predetermined amplitude the multiphase sinusoidal output signal. The synthesizer is responsive to the phase shifting output of the phase shifter so as to decrease the phase error between the source signal and output signal. When the phase error has been reduced to substantially a zero value, the output of the synthesizer will lock into a predetermined phase relationship with the source signal. The synthesized output signal can be in phase or in quadrature with the source signal. Either the positive or…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.