Process for forming a self-aligned low resistance path in semiconductor devices
US4669178A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 23, 1986 |
| Grant date | Jun 2, 1987 |
| Priority date | — |
| Expiry date | May 23, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/761
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a low resistance path, e.g., to serve as a guard ring, in a silicon semiconductor device is disclosed. An opening is defined in an upper protective layer and an underlying lower protective layer. Normally these layers are silicon nitride and silicon dioxide, respectively. The lower protective layer is isotropically wet etched so that the upper protective layer overhangs the lower protective layer and protects a part of the silicon wafer surface. A first impurity is implanted in the exposed silicon wafer surface except in the annular area protected by the upper protective layer overhang. A silicon dioxide layer is grown on the entire exposed surface of the silicon wafer which is inherently thicker over the area where the impurity has been implanted and inherently thinner over the annular area where the impurity has not been implanted. The upper protective layer is then preferably removed. A second impurity is implanted through the annular thinner silicon dioxide layer, which optionally may be etched away, to create, e.g., a guard ring in the silicon wafer around the perimeter of the thicker silicon dioxide layer which has protected the silicon wafer from the impl…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.