C-MOS logic circuit supplied with narrow width pulses converted from input pulses
US4670672A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 1985 |
| Grant date | Jun 2, 1987 |
| Priority date | — |
| Expiry date | Jan 23, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/858
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic circuit comprises an input terminal receiving an input signal of input pulses; first and second stages of C-MOS circuit formed by a first MOS FET of one channel type formed in said semiconductor substrate of one conductivity type and a second MOS FET of other channel type formed in well region of other conductivity type formed in the semiconductor substrate, said first and second stages being connected in a cascade connection; a first power terminal applying a first power voltage to the semiconductor substrate; a second power terminal applying a second power voltage to the well region; and a pulse converter converting the input signal to a pulse signal having a reference voltage of the second power voltage and short width pulses of the first power voltage produced in synchronism with the input pulses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.