Hard-wired circuit for handling screen windows
US4670752A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 19, 1985 |
| Grant date | Jun 2, 1987 |
| Priority date | — |
| Expiry date | Feb 19, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/14
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The window handler circuit is inserted between an image memory (7) having as many pages as there are possible windows and a screen controller capable of reading from any of the pages of the image memory. The handler comprises two auxiliary memories (3, 4) each of which stores bit maps in which a logic one bit indicates that the corresponding window includes an image element in the same line or the same column as the case may be as the screen position currently being scanned. A battery (5) of AND gates receives the line and column bit maps associated with the current screen position and generates a third bit map in which each logic one bit indicates that the corresponding window includes an image element at the current screen position. A priority encoder (6) then selects the visible or "uppermost" window from the said third bit map by generating the number (N) of the page to be read in the image memory (7). Relatively little memory is dedicated to determining the uppermost window at any screen position, since a two-dimensional array (the window bit map for each screen position) is generated from two one-dimensional arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.