Integrated circuit chip-and-substrate assembly
US4670770A · kind A · utility
152Cited by
9References
18Claims
0Family size
Assignees
Inventor
Key dates
| Filing date | Feb 17, 1984 |
| Grant date | Jun 2, 1987 |
| Priority date | — |
| Expiry date | Feb 17, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In the interest of enhanced yield in the manufacture of "wafer-scale" integrated circuits an assembly of integrated circuit chips is made by placing chips on a substrate. Chips have beveled edges as produced by crystallographically anisotropic chemical etching, and the substrate has wells, grooves, or openings having sloping walls. Chips are positioned on the substrate by bringing sloping walls and beveled edges in juxtaposition, and circuitry on chips is connected to circuitry on the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.