Binary data encoding and decoding process
US4672362A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1986 |
| Grant date | Jun 9, 1987 |
| Priority date | — |
| Expiry date | Apr 14, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M5/145
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A binary data encoding process comprises the steps of separating a given binary data sequence at every two bits by a serial/parallel shift register (18), and converting the separated 2-bit data into a 3-bit code by using a logic circuit (19) and a parallel/serial shift register (20). A conversion pattern in the logic circuit (19) is exclusively determined based on the 2-bit data to be converted, 1-bit data immediately before and 2-bit data immediately after said 2-bit data, and a 3-bit code converted immediately before the conversion of said 2-bit data, wherein a succession of at least one but no more than seven "0" exists between an arbitrary "1" and the succeeding "1" in the converted 3-bit code sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.