Vertical DRAM cell and method
US4673962A · kind A · utility
234Cited by
1References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 21, 1985 |
| Grant date | Jun 16, 1987 |
| Priority date | — |
| Expiry date | Mar 21, 2005 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/911
Abstract
DRAM cells and arrays of cells on a semiconductor substrate, together with methods of fabrication, are disclosed wherein the cells are formed in pairs or quartets by excavating a trench or two trenches through the cell elements to split an original cell into two or four cells during the fabrication. The cells include vertical field effect transistors and capacitors along the trench sidewalls with word lines and bit lines crossing over the cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.