Method of using complementary logic gates to test for faults in electronic components
US4674090A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 1985 |
| Grant date | Jun 16, 1987 |
| Priority date | — |
| Expiry date | Jan 28, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318321
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A pair of complementary logic gates (A and B) are used to test for faults in a group of electronic components (C1-C3) which provide respective component signals (S1-S3) indicative of their condition. One (A) of the gates ideally generates the logical OR or NOR of the component signals. The other (B) ideally generates their logical AND or NAND. The test procedure involves providing the components with information patterns that would ideally cause all the component signals to go to a logical "0" in one step and to logical "1" in another step. The actual values of the gate output signals (OA and OB) during these two steps are then compared with the respective ideal values to assess the condition of the components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.