Sequential logic circuits implemented with inverter function logic
US4675553A · kind A · utility
13Cited by
8References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 12, 1984 |
| Grant date | Jun 23, 1987 |
| Priority date | — |
| Expiry date | Mar 12, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/086
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Sequential logic circuits are implemented with inverter function logic gates. In each circuit, level shifted transistor means are utilized in place of the standard reference transistors found in ECL gate circuits so that the complement of at least one of the input signals may be included in the logical operation performed by the sequential logic circuit. The complementary clock signal is thus not required as a separate input. Sequential logic functions thus implemented have fewer gates, less complex clock drivers, consume less power and have shorter propagation delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.