FET output drive circuit with parasitic transistor inhibition
US4675561A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 15, 1985 |
| Grant date | Jun 23, 1987 |
| Priority date | — |
| Expiry date | Nov 15, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0027
Abstract
A CMOS output drive circuit has two field effect transistors (FETs) implemented with a CMOS process and characterized by parasitic bipolar transistors. The back-gates of the two transistors are tied together, such as by forming the devices in a common well, and the back-gate of the second FET is also connected to prevent its associated parasitic bipolar transistor from conducting. Quiescent loads are applied to the two FETs so that their voltages are comparable during low output loading, resulting in a drive circuit with high input impedance and high output voltage swing. The output terminal is taken from the first FET, the voltage of which becomes unbalanced from the second FET at relatively high output loads, turning on the parasitic bipolar transistor for the first FET. This gives the drive circuit a desirably high input impedance and low output impedance for heavy output loads. The circuit thus sacrifices low output impedance for high input impedance and voltage swing during light output loading when output impedance is not very important, and sacrifices high voltage swing for high input impedance and low output impedance at heavy loads at which the impedance levels are more im…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.