Dynamic RAM memory
US4675848A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 1984 |
| Grant date | Jun 23, 1987 |
| Priority date | — |
| Expiry date | Jun 18, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is provided an improved MOS dynamic random access memory (DRAM) device having an array of dynamic RAM cells accessed by word and bit lines. Each memory cell comprises a single field-effect transistor coupled by its source to the gate of an MOS storage capacitor. The word lines are coupled to their respective memory cells at the gate of the field-effect transistor therein, while the bit lines are coupled to their respective memory cells at the drain of the field-effect transistor. The bit lines are organized into pairs of adjacent polysilicon lines that are coupled to all the memory cells on both sides of the bit lines in an alternating configuration. The word lines are coupled to alternating pairs of cells on opposite sides of the word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.