Series biasing scheme for field effect transistors
US4677391A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 9, 1986 |
| Grant date | Jun 30, 1987 |
| Priority date | — |
| Expiry date | May 9, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/198
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A series biasing arrangement for a pair of junction field effect transistors (JFETs), which may be used in RF amplifiers, mixers or oscillators, comprises connecting the JFETs together in series, with the gates of the two JFETs selectively connected to different reference potentials. The first FET is also connected to the DC voltage source. In one embodiment of the invention, two operational amplifiers, whose output leads are connected to the gates of corresponding JFETs have their noninverting input leads connected to selected points on a voltage divider made up of three resistors and their inverting input leads each connected to the source of a corresponding JFET. The drain to source voltage drops across the JFETs are controlled solely by the values of two of the resistors in the three resistor voltage divider. The bias current through the series-connected JFETs can be controlled independently of the drain to source voltage drops across each of the JFETs. In either case, the two FETs need not be closely matched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.