Addressing circuit for a matrix display incorporating shift registers formed from static memories and addressing process using such a circuit
US4677594A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 1985 |
| Grant date | Jun 30, 1987 |
| Priority date | — |
| Expiry date | Jan 30, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G3/2011
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Addressing circuit for a matrix display having shift registers formed by static memories and process for addressing with such a circuit. For a display with p columns, the circuit comprises p register points formed by static memories (M.sub.i), a first series of switches (C.sub.1) placed in front of the register points M.sub.k-1, k being an even number between 1 and p, a second series of switches (C.sub.2) placed in front of the register points M.sub.k and a transfer clock (13) producing a first signal (.phi..sub.1) controlling the first series of switches, in order to ensure the loading of a "1" signal into the register point (M.sub.1) and the transfer of the content of register point M.sub.k to register point M.sub.k+1, and a second signal (.phi..sub.2) controlling the second series of switches for ensuring the transfer of the content of register point M.sub.k-1 to register point M.sub.k.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.