Self-aligned inlay transistor with or without source and drain self-aligned metallization extensions
US4677736A · kind A · utility
36Cited by
5References
31Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 17, 1986 |
| Grant date | Jul 7, 1987 |
| Priority date | — |
| Expiry date | Apr 17, 2006 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/945
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A self-aligned process is described for depositing gate electrode material in an inlay field effect transistor. The process particularly provides means for inclusion of lightly doped source and drain extensions to minimize high field effects in the channel region. The process described herein is also particularly useful for providing source and drain contact metal which also acts as an ion implantation mask layer during several of the process steps. The method described herein is usable in conventional VLSI fabrication production facilities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.