Sequential access LSI memory circuit for pattern generator
US4679173A · kind A · utility
24Cited by
3References
2Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 12, 1985 |
| Grant date | Jul 7, 1987 |
| Priority date | — |
| Expiry date | Mar 12, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an LSI memory of the invention, in order to decrease the number of input address lines, an address counter having a bit length corresponding to some input address lines is incorporated in the LSI memory to compensate for the number of omitted input address lines. The address counter is counted up in response to a clock pulse supplied through an additional clock input signal line and is initialized in response to a chip enable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.