Virtual memory address translation mechanism with combined hash address table and inverted page table
US4680700A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1986 |
| Grant date | Jul 14, 1987 |
| Priority date | — |
| Expiry date | Dec 19, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A virtual memory address translation mechanism is provided for converting virtual memory addresses provided by a CPU into real memory addresses within page frames in a large hierachial memory wherein the real memory space is substantially smaller than the scope of the virtual memory. The conversion or translation mechanism includes a combined table in the memory which includes a first list covering the respective virtual address of each memory address (Inverted Page Table or IPT) and a second list connecting each of a plurality of hashed addresses with a predetermined initial virtual address of a linked group of virtual addresses, each of which when hashed produces the connected hashed address (Hashed Addressed Table, HAT). The system also has means for hashing a selected virtual address to produce a hashed address. Also included is apparatus for sequentially searching through the linked group of virtual addresses in the combined table until a selected virtual address is located as well as apparatus responsive to the location of a particular selected virtual address for accessing from the first list, the real memory address of the located virtual address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.