Semiconductor memory device
US4680734A · kind A · utility
5Cited by
2References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 5, 1985 |
| Grant date | Jul 14, 1987 |
| Priority date | — |
| Expiry date | Aug 5, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having a data inverting circuit for selectively inverting an input/outpt data of a sense amplifier in such a way that the charging states of respective memory cells connected to two bit lines in each bit line pair become equal for the same input/output data. A clamp circuit draws the potentials of all of the bit lines to a predetermined potential in response to a clear control signal, whereby the contents of all of the memory cells are cleared at the same time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.