Distributed clock synchronization in a digital data switching system
US4680779A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 14, 1985 |
| Grant date | Jul 14, 1987 |
| Priority date | — |
| Expiry date | Jan 14, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A clock synchronization system in a digital data switching system, such as a digital PBX. The system has a local clock generating timing signals at a frequency greater than a nominal frequency, a circuit for lowering the local clock frequency and a comparator coupled to a second clock operating substantially at the nominal frequency for activating the lowering circuit so that the local clock is synchronized with the second clock. The system is distributed by placing the local clock and the lowering frequency on the control module of the switching system and placing the comparator to one or more of the line card modules which is receiving the second clock signals. Communication between the comparator and lowering circuit may be over a single line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.