Planarization of metal films for multilevel interconnects
US4681795A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 23, 1985 |
| Grant date | Jul 21, 1987 |
| Priority date | — |
| Expiry date | Aug 23, 2005 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24917
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In the fabrication of multilevel integrated circuits, each metal layer is anarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.