Gate array cell
US4682201A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 14, 1986 |
| Grant date | Jul 21, 1987 |
| Priority date | — |
| Expiry date | Jul 14, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/907
Abstract
A gate array layout in which alternative rows include areas of devices of the same diffusion type, and all the rows run in parallel on the device. However, the diffusion areas in adjacent rows are offset with respect to one another so that only cells in alternative rows which are all of one conductivity define straight parallel columns. By providing this relative offset between adjacent rows, the contacts to the source, drain and gate of interconnected devices all lie on straight lines, thereby simplifying the metal interconnect patterns. In addition to cells along each row being immediately abutting, cells in adjacent rows are abutting (although offset with respect to each other) so that no routing channels need be reserved. By offset, it is meant that the cells of both N and P type conductivity devices each contain the same number of transistor, or source and drain diffusions lying along a given row; but at least one of the source and drain diffusions in each cell does not lie in a column with the adjacent diffusion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.