Logarithmic arithmetic logic unit
US4682302A · kind A · utility
89Cited by
2References
11Claims
0Family size
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Inventor
Key dates
| Filing date | Dec 14, 1984 |
| Grant date | Jul 21, 1987 |
| Priority date | — |
| Expiry date | Dec 14, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3868
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a digital signal processing system, a logarithmic arithmetic logic unit is provided which selectively performs multiply/accumulate operations of operands in logarithmic number representation. Direct feed through of operands through an adder/subtractor circuit, even when an addition or subtraction is not effected, eliminates external bypass circuitry. A method for adding and subtracting operands in logarithmic number representation is provided. An adder/subtractor circuit which efficiently effects addition and subtraction of operands in logarithmic number representation over a wide dynamic range is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.