MOSFET process using implantation through silicon
US4682404A · kind A · utility
20Cited by
12References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 23, 1986 |
| Grant date | Jul 28, 1987 |
| Priority date | — |
| Expiry date | Oct 23, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/371
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A simplified small geometry MOS process incorporates a tungsten shunt layer on the thin silicon gate electrode layer allowing reduction of the thickness of the silicon layer and the use of an implant through the layer to form precisely controlled shallow source/drain regions without channeling. Lightly doped extension of the source and drain regions are automatically formed by an LDD implant following an isotropic undercutting etch of the silicon. The process is readily adapted to optional guard band implants and other beneficial structures such as gate sidewall oxide spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.