Testable, fault-tolerant power interface circuit for normally de-energized loads
US4683105A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 31, 1985 |
| Grant date | Jul 28, 1987 |
| Priority date | — |
| Expiry date | Oct 31, 2005 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E30/30
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A power interface circuit for normally deenergized loads includes the capability to test the operation and connections thereof without any possibility of accidental activation of the load. Three input signals may be received by the power interface circuit which supplies power to a load if two out of three of the input signals indicates activation of the load. A normally closed switch which ordinarily provides power directly to the voter is opened during testing so that the voter is supplied with a reduced power that is insufficient to activate the load. The normally closed switch is closed if any of the input signals indicate activation of the load. Current sensors are included in the power interface circuit to detect all possible logic combinations for activating the load and to detect the operation of the normally closed switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.