dRAM cell and array
US4683486A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 24, 1984 |
| Grant date | Jul 28, 1987 |
| Priority date | — |
| Expiry date | Sep 24, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/395
Abstract
A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with both the transistor and the capacitor formed in a trench in a substrate. The transistor source, channel, and drain and one capacitor plate are formed in a layer of material inserted into the trench and insulated from the substrate; the gate and other capacitor plate are formed in the substrate trench sidewall. In preferred embodiments bit lines on the substrate surface connect to the inserted layer, and word lines on the substrate surface are formed as diffusions in the substrate which also form the gate. The trenches and cells are formed in the crossings of bit lines and word lines; the bit lines and the word lines form perpendicular sets of parallel lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.