Latch-up resistant CMOS structure for VLSI including retrograded wells

US4683488A · kind A · utility

Assignee

• Hughes Aircraft Company · US

Inventors

• William W. Lee · Arcadia, US
• Kuang-Yeh Chang · Taipei, TW

Key dates

• Filing date: Feb 28, 1986
• Grant date: Jul 28, 1987
• Expiry date: Feb 28, 2006

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/854

Abstract

A complementary metal oxide semiconductor (CMOS) structure having the source and drain regions of individual transistor devices separated from the peak impurity concentrations of the respective N- and P-wells of such devices. The CMOS structure includes trenches between the individual transistor devices, and highly doped field regions are formed in the bottom of the trenches. Each N- and P-well includes a retrograde impurity concentration profile and extends beneath adjacent trenches.