Method and apparatus for interfacing buses of different sizes
US4683534A · kind A · utility
83Cited by
6References
4Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 17, 1985 |
| Grant date | Jul 28, 1987 |
| Priority date | — |
| Expiry date | Jun 17, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a data processing system having a first bus sized to accomodate 2.sup.x units of data and a second bus sized to accomodate 2.sup.y units of data, where x and y are positive integers and y is less than or equal to x, a method and apparatus for determining y from the x least significant bits of a control address, concatenated with a decode control bit, and then decoding the (x-y) most significant bits of the x control address bits to determine which of x data unit transceivers coupled between the first and second buses should be enabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.