Binary MOS ripple-carry parallel adder/subtracter and adder/subtracter stage suitable therefor
US4683548A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 24, 1985 |
| Grant date | Jul 28, 1987 |
| Priority date | — |
| Expiry date | Sep 24, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/388
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The adder/subtracter disclosed sums a plurality of n-digit binary-coded numbers (A, B, C . . . Z) successively by forming corresponding partial sums (Sb, Sc . . . Sz) according to the following recursive formula: EQU A+B+C . . . +Z=((A+B)+C) . . . +Z=(Sb+C) . . . +Z=Sc . . . +Z=Sz. The partial sums are formed by means of parallel adders/subtracters which, in turn, include adder/subtracter stages. Each of the stages is formed by a full adder and a switching section which forms the ones complement of the subtrahend in case of subtraction. The inputs of the parallel adder/subtracter for the first partial sum are preceded by series-connected like delay elements beginning with the second lowest weight and increasing by one from weight to weight, the delay provided by the delay elements being equal to the time required to generate the carry of the full adder. Beginning with the next to the last stage of the parallel adder/subtracter, additional like delay elements are connected in series between the output of the stages and the sum output terminal, which also increase by one from stage to stage. Additional delay elements and transfer stages may be placed between the switching section and…
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