Simplified cache with automatic update
US4685082A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 1985 |
| Grant date | Aug 4, 1987 |
| Priority date | — |
| Expiry date | Feb 22, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0835
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A simplified cache with automatic updating for use in a memory system. The cache and the main memory receive data from a common input, and when a memory write operation is performed on data stored at a memory location for which there is a corresponding cache location, the data is written simultaneously to the cache and to the main memory. Since a cache location coresponding to a memory location always contains a copy of the data at the memory location, there is no need for dirty bits or valid bits in the cache resisters and the associated logic in the cache control. The main memory used with the invention may receive data either from a CPU or from I/O devices, and the cache includes apparatus permitting the CPU to perform cache read operations while the main memory is receiving data from an I/O device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.