Minimum delay high speed bus driver
US4686396A · kind A · utility
12Cited by
5References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 26, 1985 |
| Grant date | Aug 11, 1987 |
| Priority date | — |
| Expiry date | Aug 26, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09429
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A minimum delay, high speed, tri-state bus driver is utilized to couple data and control signals to a memory bus with a minimum amount of buffering. Two transistors 24, 26, utilized in a bootstrap configuration, deliver a system clock to the gate terminals of output transistors 28, 30 which are coupled to the memory bus 40. The input data signals and accompanying control signals are applied to these bootstrap transistors 24, 26 via push/pull amplifiers 20, 22 and, depending on the data level of the input data signal, either a logic 1, a logic 0, or a high impedance open circuit is applied to the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.