Test apparatus for testing a multilevel cache system with graceful degradation capability
US4686621A · kind A · utility
39Cited by
6References
29Claims
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Key dates
| Filing date | Jun 30, 1983 |
| Grant date | Aug 11, 1987 |
| Priority date | — |
| Expiry date | Jun 30, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multilevel set associative cache system whose directory and cache store are organized into levels of memory locations includes control apparatus which selectively degrades cache operation in response to error signals from directory error checking circuits to those levels detected to be free from errors. Test apparatus coupled to the control apparatus and operates to selectively alter the operational states of the cache levels in response to commands received from a central processing unit for enabling testing of such control apparatus in addition to the other cache control areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.