Logic cell placement method in computer-aided-customization of universal arrays and resulting integrated circuit
US4686629A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 1986 |
| Grant date | Aug 11, 1987 |
| Priority date | — |
| Expiry date | Jul 21, 2006 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/923
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved automatic placement process for placing logic cells in a universal array. Unused basic units are assigned to rows to reduce the congestion of the wiring in high congestion regions of a universal array. These assigned unused basic units are allocated among rows in a pyramidal manner. Those unused basic units allocated to a given row are distributed along that row in a manner to reduce wiring congestion. During a pair exchange portion of the placement process, quality criteria used for deciding whether to exchange two logic cells on different rows include skipped rows in a node, y-span of a node, minimizing the number of logic cells in excess of two in a node on a row, making a longest row shorter and making longer a shortest row or one which is within a tolerance of being a shortest row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.