Synchronous data receiver circuit
US4686690A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 20, 1985 |
| Grant date | Aug 11, 1987 |
| Priority date | — |
| Expiry date | Jun 20, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/046
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The synchronous data receiver circuit, after temporarily storing received data in a data memory having a large enough capacity to store at least two frames, detects a frame synchronization signal pattern with a pattern match circuit, then stores the message data alone of the received data in a data buffer, detects errors with a decoder and checks whether the detected frame synchronization signal pattern is the correct pattern of the frame synchronization signal or a wrong frame synchronization signal pattern contained in the message data. If it is the correct frame synchronization signal, the message data is sent to a data processing unit at the next stage or, if it is a wrong frame synchronization signal pattern, the frame synchronization signal pattern is checked again from the next data on.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.