Three-dimensional CMOS using selective epitaxial growth
US4686758A · kind A · utility
57Cited by
4References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 2, 1986 |
| Grant date | Aug 18, 1987 |
| Priority date | — |
| Expiry date | Jan 2, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional CMOS integrated circuit structure in which two complementary field effect transistors are fabricated in vertical alignment with one another, and in which both transistors are single crystal and share a common crystal lattice structure and form a single unitary crystalline structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.