Bit processing utilizing a row and column ladder sequence
US4688193A · kind A · utility
5Cited by
9References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 27, 1984 |
| Grant date | Aug 18, 1987 |
| Priority date | — |
| Expiry date | Jul 27, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05B2219/13082
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A relay ladder sequence circuitry having i columns and j rows is divided into a plurality of sections each having a predetermined number of rows, and the bit informations are processed in a parallel manner in the rows of the sections. More specifically, the program in accordance with the sequence ladder construction is memorized and are successively read out as the addresses of the program are appointed. The signals of relay contacts as the bit information are processed for each line in accordance with the read out program, so that a high processing speed is attained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.